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ADP3121
Another consideration is the nonoverlap circuitry of the
ADP3121 that attempts to minimize the nonoverlap period.
During the state of the high ? side turning off to low ? side
turning on, the SW pin is monitored (as well as the
conditions of SW prior to switching) to adequately prevent
overlap.
However, during the low ? side turn ? off to high ? side
turn ? on, the SW pin does not contain information for
determining the proper switching time, so the state of the
Figure 2 shows an example of the typical land patterns
based on the guidelines given previously. For more detailed
layout guidelines for a complete CPU voltage regulator
subsystem, refer to the PC Board Layout Considerations
section of the ADP3188 data sheet.
C BST1
DRVL pin is monitored to go below one sixth of V CC ; then,
a delay is added. Due to the Miller capacitance and internal
delays of the low ? side MOSFET gate, ensure that the
Miller ? to ? input capacitance ratio is low enough, and that the
low ? side MOSFET internal delays are not so large as to
allow accidental turn ? on of the low ? side when the high ? side
turns on. Contact ON Semiconductor for an updated list of
recommended low ? side MOSFETs.
PC Board Layout Considerations
Use these general guidelines when designing printed
C BST2
R BST
circuit boards:
? Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
? Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.
? Connect the PGND pin of the ADP3121 as closely as
possible to the source of the lower MOSFET.
? Locate the V CC bypass capacitor as close as possible to
the V CC and PGND pins.
? Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
http://onsemi.com
7
C VCC
Figure 2. External Component
Placement Example
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